1. Field of the Invention
The present invention relates generally to integrated circuits and, more specifically, to performance optimization based on specific conditions under which an individual integrated circuit is being operated.
2. Description of the Related Art
Integrated memory in fine-line (e.g., 45-nm or 65-nm CMOS) process technologies is aimed to deliver high-quality performance at relatively low power levels and supply voltages. However, intrinsic integrated circuit (IC) characteristics associated with these process technologies make it difficult to design memories that meet these requirements. More specifically, strenuous constraints are imposed on IC design by one or more of local random mismatch of circuit components, relatively high device sub-threshold leakage currents, global process variations, and relatively wide operating temperature and voltage ranges. Disadvantageously, these constraints tend to (i) cause an integrated memory to occupy a relatively large area on the chip, have relatively high power consumption, and have compromised performance and/or (ii) cause the IC yield to be relatively low.